1. Field of the Invention
This invention relates to a semiconductor device having at least one high-voltage transistor whose output circuit is applied with higher voltage than the power supply voltage.
This invention also relates to a semiconductor device which is a heating resistance drive IC for heat-sensitive paper, a liquid crystal drive IC or the like having multiple high-voltage transistors whose output circuits are applied with higher voltage than the power supply voltage.
This invention also relates to a structure for a MOS transistor and a semiconductor integrated circuit device including the MOS transistor, more particularly to a structure for electrically isolating a MOS transistor.
This invention also relates to a semifinished silicon water product comprising extremely fine chips which is usable for production of document reading ICs for use in fax machines and thermal transfer ICs.
2. Prior Art
FIG. 2 shows the electrical circuit of a prior-art thermal head driver IC for passing a current of about 10 Ma through resistances for heating heat-sensitive paper. Multiple output pads 11 are provided along the edge of the semiconductor device chip. The pads are connected with drive transistor TD1-TDN. The gates of the transistors TD1-TDN are applied with voltage by a driver control circuit 12. The driver control circuit 12 operates at the power supply voltage. The heat-sensitive paper resistances are connected in series with the pads. A high voltage (about 35 V) is applied to the heat-sensitive paper resistances. When a transistor turns ON, a current of 10 mA passes through the associated resistance and the heat-sensitive paper is discolored by the Joule heat of the resistance.
In the prior-art semiconductor device with CMOS circuitry, the low-voltage MOSFETs used in the driver control circuit are constituted as protective transistors for preventing breakdown of the output circuit by static electricity from the pad terminals. An N.sup.+ -type source region and drain region are formed on the surface of a P-type silicon substrate and the gate is formed on a gate oxide film on the semiconductor substrate surface between the source region and the drain region, The drain region is electrically connected to the pad terminal by a wire. The source region and gate are electrically connected to the vss terminal of the power supply by a wire. When static electricity appears on a pad terminal, breakdown of the internal semiconductor elements is prevented by discharging it through this protective transistor.
In the heat-sensitive paper type printer, for example, high-voltage MOS transistors of the structure shown in FIG. 3 are used as the drive transistors of the thermal head IC for driving the heating resistances. Specifically, an N.sup.+ -type source region 4 and drain region 5 are formed on the surface of a single-crystal P-type silicon substrate 1. To obtain a high-withstand-voltage characteristic, a low-concentration drain region 21 is formed under a field insulating film 7 to be in contact with the drain region 5. The channel-forming region is the surface of the substrate 1 between the source region 4 and the drain region 21. The impedance of the channel-forming region is controlled by a gate 8 formed on the substrate 1 via a gate insulating film 6.
In the case of an IC for driving heating resistances, the drain withstand voltage is 30-50 V. The gate insulating film 6 is therefore formed as a silicon oxide film having a thickness of 500-1500 .ANG.. The assignee earlier developed and applied for patent on an IC with a thin gate insulating film (see Japanese Patent Application Public Disclosure No. Hei 7-226505).
When the drive control circuit uses CMOS construction, the transistors of one conductivity type are formed in well regions constituting deep diffused regions. In this case, the wells are separated by long distances to electrically isolate them from each other. FIG. 4 is a sectional view showing the structure used for well isolation in the ordinary prior-art semiconductor integrated circuit device. Nwells 101, 102 are formed in the vicinity of the surface of a P-type semiconductor substrate 100 at a spacing of about 8 .mu.m and a LOCOS 103 is formed between the Nwells 101, 102 to electrically isolate them from each other. In addition, each of the Nwells 101 and 102 is formed near the surface thereof with a MOS transistor consisting of a P.sup.+ -type drain 104, source 105 and polyslicon gate 106. The P-type semiconductor substrate 100 has a resistivity of 20-30 .OMEGA..multidot.cm and an Nwell ion implantation concentration of 4.times.10.sup.12 /cm.sup.2, and is thermally diffused at 1150.degree. C., 6H.
In the prior-art semiconductor device, however, the electrostatic withstand voltage decreases with decreasing transistor size.
Moreover, the prior-art semiconductor device having protective transistors cannot be applied to a semiconductor device whose output circuit operates at a voltage above 20 V because the drain withstand voltage of the protective transistors is below 20 V. In addition, attempts to increase the withstand voltage have complicated the fabrication process.
In the prior-art high-voltage MOS transistor, the shallow diffusion depth of the low-concentration drain region for obtaining the high-voltage characteristic has high resistance so that the area of the transistor has to be made large for enabling passage of a large current. An attempt to overcome this problem by increasing the concentration of the drain region 21 so as to lower its resistance causes the drain withstand voltage to fall below 10 V. If an attempt is made to solve it by increasing the diffusion depth while maintaining the low-concentration, the drain region 21 also becomes large in the lateral direction, resulting in a large transistor.
On the other hand, the MOS transistor with the Nwell drain structure used to obtain a high withstand voltage involves an Nwell isolation technology problem. The problem is that, owing to the long the lateral diffusion length of the Nwells, the distance between adjacent Nwells has to be at least twice the diffusion length. Moreover, since the impurity concentration of the P-type regions between adjacent Nwells is low, the depletion layer spreads widely during low voltage application, so that the Nwell spacing has to be at least twice the width of the depletion layer during application of the power supply voltage.
In addition, the semiconductor device integrating high-voltage MOS transistors and low-voltage. MOS transistors requires a photolithographic step for forming the low-concentration drain regions of the high-voltage MOS transistors. In other words, one more photolithographic step is required than in the case of integrating only ordinary low-voltage MOS transistors.
The difficulty of reducing cost has also been a problem when very thin ICs are aligned in an IC module, since the nature of the application makes it impossible to shorten the IC length. If the IC width is reduced, there is a problem that a nondefective product may be marked as a defective one owing to the large size of the bad mark and the low positioning accuracy. Furthermore, since ICs are ordinarily flat, it has not been possible to package them in a cylindrical IC module.